Weekly ranking, Technology

Qwenputer: a fully functioning, deterministic RISC-V CPU inside Qwen3.5

Divyansh Agrawal, divagr.com, Technology

A substantial original build that compiles a working RV32IM CPU into Qwen3.5 weights. It backs the claim with its own validation and benchmark numbers, though readers cannot check them here.

What it adds

Shows Qwen3.5's Gated DeltaNet layers can be hand-set into exact RAM, then compiles a verified RISC-V CPU and filesystem into the model, with benchmarks showing tool-level arithmetic accuracy and unchanged normal text.

Claim by claim

• 14 the author's own
• 0 an AI would say
• 0 known elsewhere
• 2 common knowledge

Its strongest original claims

• Setting the GDN gate to 1, beta to 1 and using one-hot keys makes every write overwrite exactly one row and every one-hot query retrieve an exact value, turning GDN into exact RAM.
• A compiler sets every weight directly, with no training, turning a CPU circuit description into transformer layer pieces.
• Each instruction becomes ADDR, VAL and STEP tokens forming the CPU's execution trace during decoding.
• The CPU is a 32-bit RV32IM core with Zba and a bignum unit, occupying 11 layers in front of Qwen's 32.
• The CPU passes riscv-tests, matches qemu, and ran 18 million instructions free-running without error.

Scored by Expulp Verdict for what the piece adds beyond what is already known and published. The full verdict shows every claim with its reasons. Leaderboard, what Verdict gets right and where it is weak.